The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device having a ferroelectric capacitor.
Semiconductor devices such as DRAMs and SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory device. These conventional semiconductor devices, however, are volatile in nature and the information stored therein is lost when the electric power is turned off. Thus, it has been practiced in conventional computers and computer systems to use magnetic disk devices as a large capacity, auxiliary storage device for storing programs and data.
However, magnetic disk devices are bulky and fragile, and are inherently vulnerable to mechanical shocks. Further, magnetic disk devices generally have drawbacks of large electrical power consumption and low access speed.
In view of the problems noted above, there is an increasing tendency in computers and computer systems of using flash-memory devices for the non-volatile auxiliary storage device. A flash-memory device is a device having a construction similar to that of a MOS transistor and stores information in an insulated floating gate in the form of electrical charges. It should be noted that flash-memory devices have a construction suitable for monolithic integration on a semiconductor chip in the form of an LSI. Thus, there are attempts to construct a large-capacity storage device comparable to a magnetic disk device by using a flash-memory.
In a flash-memory device, writing of information is achieved by tunneling of hot electrons through a tunneling insulation film into the floating gate electrode. Further, erasing of the information is achieved also by causing the electrons in the floating gate to tunnel to a source region or to a channel region through the tunneling insulation film. Thus, a flash-memory device has an inherent drawback in that it takes a substantial time for writing or erasing information. Further, a flash-memory device generally shows the problem of deterioration of the tunneling insulation film after a repeated writing and erasing operations. When the tunneling insulation film is deteriorated, the reading or erasing operation becomes unstable and unreliable. An EEPROM, having a similar construction to a flash-memory, has a similar problem.
In view of the various drawbacks of the foregoing conventional non-volatile semiconductor devices, there is a proposal of a ferroelectric semiconductor memory device designated hereinafter as FeRAM for the auxiliary memory device and further for the high-speed main memory device of a computer. A ferroelectric semiconductor memory device stores information in a ferroelectric capacitor insulation film in the form of spontaneous polarization.
A ferroelectric semiconductor memory device typically includes a memory cell transistor and a memory cell capacitor similarly to a DRAM, wherein the memory cell capacitor uses a ferroelectric material such as PZT (Pb(Zr,Ti)O3) or PLZT ((Pb,La)(Zr,Ti)O3) for the capacitor insulation film. Thus, the ferroelectric semiconductor memory device is suitable for monolithic integration to form an LSI.
As the ferroelectric semiconductor memory device carries out writing of information by controlling the spontaneous polarization of the ferroelectric capacitor insulation film, the writing operation is achieved with high speed, faster by a factor of 1000 or more than the case of a flash-memory. As noted before, the writing of information is achieved in a flash-memory by injecting hot electrons into the floating gate through the tunneling insulation film. As the control of the polarization is achieved by simply applying a voltage, the power consumption is also reduced below about {fraction (1/10)} as compared with the case of a flash-memory. Further, the ferroelectric semiconductor memory device, lacking the tunneling insulation film, provides an increased lifetime of one hundred thousand times as large as the lifetime of a flash-memory device.
FIG. 1 shows the construction of a conventional FeRAM 10.
Referring to FIG. 1, the FeRAM 10 includes a memory cell transistor constructed on a Si substrate 11, which may be any of the p-type or n-type. The half of the cell structure is represented in FIG. 1, wherein it should be noted that the process used in FIG. 1 is nothing more than an ordinary CMOS process. Thus, a p-type well 11A is formed on a Si substrate 11, on which an active region is defined by a field oxide film 12. On the Si substrate 11, there is provided a gate electrode 13 in correspondence to the foregoing active region, wherein the gate electrode 13 constitutes the word line of the FeRAM. Further, a gate oxide film not illustrated is interposed between the Si substrate 11 and the gate electrode 13, and diffusion regions 11B and 11C of the n+-type are formed in the p-type well 11A at both lateral sides of the gate electrode 13 as the source region and the drain region of the memory cell transistor. Thereby, a channel region is formed in the p-type well 11A between the diffusion region 11B and the diffusion region 11C.
It should be noted that the gate electrode 13 is covered by a CVD oxide film 14 provided so as to cover the surface of the Si substrate 11 in correspondence to the active region. A lower electrode 15 having a Pt/Ti structure is deposited on the CVD oxide film 14, wherein the lower electrode 15 constitutes the drive line of the FeRAM. A ferroelectric capacitor insulation film 16 of PZT or PLZT covers the lower electrode 15, and an upper electrode 17 of Pt is formed on the ferroelectric capacitor insulation film 16.
It should be noted that the lower electrode 15, the ferroelectric capacitor insulation film 16 and the upper electrode 17 form together a ferroelectric capacitor. The ferroelectric capacitor as a whole is covered by another interlayer insulation film 18.
The contact hole 18A is formed in the interlayer insulation film 18 so as to expose the upper electrode pattern 17, and contact holes 18B and 18C are formed further in the interlayer insulation film 18 and 14 so as to expose the diffusion regions 11B and 11C, respectively.
The local interconnection pattern 19A is formed by an Al-alloy such that the local interconnection pattern 19A connects the contact hole 18A and the contact hole 18B electrically.
There is provided a bit line pattern 19B of an Al-alloy on the interlayer insulation film 18 so as to make an electrical contact with the diffusion region 11C at the contact hole 18C. The local interconnection pattern 19A and the bit line 19B are covered by a passivation film 20.
In such an FeRAM, it is important to maximize the switching electric charge of the ferroelectric capacitor insulation film 16 and minimize the leakage current. Further, it is necessary that the ferroelectric capacitor insulation film 16 maintains the initial switching electric charge over a long period of time.
In order to maximize the switching electric charge, it is practiced conventionally to deposit the ferroelectric capacitor insulation film 16 by a sputtering process in the form of an amorphous phase and apply a crystallization process in an O2 atmosphere.
In order to maintain the large switching electric charge for the ferroelectric capacitor insulation film 16, it is further desired to form the upper electrode 17 in an oxidizing atmosphere so as to avoid formation of oxygen defect in the ferroelectric capacitor insulation film. Thus, there is a proposal to use a conductive oxide such as IrO2 for the upper electrode 17 in place of Pt.
It turned out, however, that a ferroelectric capacitor having the ferroelectric capacitor insulation film 16 of PZT in combination with the upper electrode of IrO2 raises a problem of aging of the PZT film 16 in that the value of the switching electric charge decreases with time. In order to avoid this aging problem, it has been necessary to dope the PZT film 16 with Ca and Sr with a substantial amount, while such a doping of the PZT film 16 invites a decrease in the value of the switching electric charge.
In view of the foregoing, investigations have been made on an FeRAM in which a ferroelectric capacitor insulation film of a sputtered PZT film is combined with an upper electrode of SrRuO3. It turned out, however, that the ferroelectric capacitor of the foregoing construction, while being able to suppress the aging, suffers from the problem of large leakage current. With regard to the degradation of the leakage characteristic of a PZT film combined with an upper electrode of IrO2 or SrRuO3, reference should be made to Stolichnov, I., et al., xe2x80x9cELECTRICAL TRANSPORT PROPERTIES OF Pb(Zr,Ti)O3/OXIDE ELECTRODE INTERFACE, 9th European Meeting on Ferroelectricity, Praha, Czech Republic, Jul. 12, 1999.
Accordingly, it is a general object of the present invention to provide a novel and ferroelectric random access memory wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a ferroelectric random access memory having a reduced leakage current for a ferroelectric capacitor used therein.
Another object of the present invention is to provide a ferroelectric random access memory, comprising:
a substrate carrying thereon an active device;
a lower electrode provided over said substrate in electrical connection with said active layer;
a ferroelectric film containing at least Pb, Zr and Ti and having a perovskite structure, said ferroelectric film comprising a number of crystal grains extending continuously from a bottom surface to a top surface of said ferroelectric film and forming a columnar microstructure, said crystal grains having pinholes of a size of several ten nanometers; and
an upper electrode of a conductive oxide film provided on said ferroelectric film, said upper electrode having a perovskite structure and containing therein Sr and Ru,
said ferroelectric film further containing Ca and Sr,
said ferroelectric film including said pinholes with a density not exceeding 34/xcexcm2.
Another object of the present invention is to provide a method of fabricating a ferroelectric random access memory comprising the steps of:
depositing a ferroelectric film having a perovskite structure on a lower electrode by a sputtering process that uses a target containing therein at least Pb, Zr, Ti, Ca and Sr;
annealing said ferroelectric film in a first, inert atmosphere that contains O2 with a reduced partial pressure;
annealing said ferroelectric film, after said step of annealing in said first atmosphere, in a second, oxidizing atmosphere;
depositing, after said step of annealing in said second atmosphere, a conductive film having a perovskite structure and containing therein Sr and Ru on said ferroelectric film,
said target containing Ca and Sr with respective concentrations, normalized to a sum of Zr and Ti atoms in said target, such that said concentration of Ca does not exceed 0.035 and such that said concentration of Sr does not exceed 0.025.
According to the present invention, the leakage current flowing through the ferroelectric film is minimized by controlling the pinhole density in the ferroelectric film to be less than 34 xcexcm2, preferably about 17/xcexcm2, or less. In view of the fact that such a decrease of the pinhole density is achieved by decreasing the content of Ca and Sr in the ferroelectric film, the ferroelectric capacitor of the present invention can provide a large value for the switching electric charge. In the present invention, the problem of aging of the ferroelectric film is successfully avoided even when the Ca and Sr contents are reduced in the ferroelectric film due to the fact that both the ferroelectric film and the upper electrode have the perovskite structure and that the degree of lattice misfit between the ferroelectric film and the upper electrode is reduced as compared with the case of using IrO2 for the upper electrode.
Another object of the present invention is to provide a method of fabricating a ferroelectric random access memory, comprising the steps of:
depositing a ferroelectric film containing Pb, Zr and Ti on a lower electrode by a sputtering process;
annealing said ferroelectric film in a first, inert atmosphere that contains O2 with a reduced partial pressure;
depositing an upper electrode of a conductive film having a perovskite structure and containing Sr and Ru therein on said ferroelectric film; and
annealing said ferroelectric film and said upper electrode in a second, oxidizing atmosphere.
According to the present invention, the upper electrode is formed on the ferroelectric film prior to the annealing process conducted in the oxidizing atmosphere and hence prior to the formation of pinholes in the ferroelectric film. Further, the formation of pinholes in the ferroelectric film is suppressed as a result of conducting the second annealing process while mechanically holding the top surface of the ferroelectric film by the upper electrode. The ferroelectric film thus processed has a characteristic flat and smooth top surface.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.